1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a MOS transistor in an electrostatic discharge protection circuit that protects an internal circuitry comprising MOS transistors from an electrostatic discharge damage.
This application relies for priority on Japanese patent application, Serial Number 187750/1998 filed Jul. 2, 1998, which is incorporated herein by reference in its entirety.
2. Description of the Related Art
In general, a MOS transistor is used for a logic circuit. The MOS transistor is also used as an element for an electrostatic discharge protection circuit formed in an area close to a signal input/output circuit or the like. The MOS transistor prevents circuitry from breaking due to an electrostatic discharge from an external environment.
FIG. 1 is a circuit diagram showing the protection circuit.
The protection circuit includes a PMOS transistor 200 and an NMOS transistor 202, and is located at an input side of an internal circuitry 206 or the like (for example, a logic circuit), which includes MOS transistors. A drain of the PMOS transistor 200 is connected to a drain of the NMOS transistor 202. A source, a gate, and a substrate (i.e., a back gate or a bulk) of the PMOS transistor 200 are commonly connected to one another and are supplied with a power supply voltage VDD. A source, a gate, and a substrate (i.e., a back gate or a bulk) of the NMOS transistor 202 are commonly connected to one another and maintained at a ground voltage GND. A node P, which is connected to the PMOS transistor 200 and the NMOS transistor 202, is connected to a pad 204 and the internal circuitry 206.
In a general MOS transistor structure, a parasitic bipolar transistor is present in which the source of the MOS transistor forms an emitter, the drain of the MOS transistor forms a collector and the substrate of the MOS transistor forms a base. As shown in FIG. 1, the behavior of the MOS transistors which functions as protection elements is as follows. In the case of the NMOS transistor 202 as an example, when the electrostatic voltage (i.e., a surge voltage) having positive polarity is applied to an n-type drain diffusion layer of the NMOS transistor 202 through the node P, an avalanche breakdown occurs at a p-n junction between the n-type drain diffusion layer and a p-type substrate. At this time, an avalanche current results from the avalanche breakdown and the current flows into the substrate. Since a voltage potential of the substrate is raised by the avalanche current, a junction between an n-type source diffusion layer and the p-type substrate become conductive. Then, the NPN parasitic bipolar transistor, which is formed by the NMOS transistor 202 used as the protection element, begins to conduct. As a result, a withstanding voltage (i.e., a break down voltage) of the protection element is indicated as an emitter-collector withstanding voltage BVceo of the parasitic bipolar transistor. Since the emitter-collector withstanding voltage BVceo is set at a predetermined value that is smaller than that of a withstanding voltage BVsd of the MOS transistor in the internal circuitry 206, the breakdown caused by the surge voltage occurs only at the protect element. Therefore, a surge current caused by the surge voltage flows to the ground voltage GND through the NMOS transistor 202.
As explained above, the protection element using the MOS transistor protects the internal circuitry 206 from the surge voltage by utilizing the parasitic bipolar transistor.
In the above described protection element, the surge current spreads toward the gate width direction. The gate width is enlarged to decrease a current density per unit gate width, and so a heat malfunction (i.e., a thermal runaway) caused by the current crowding is prevented and the withstanding voltage against the electrostatic discharge is improved.
However, in order to satisfy the withstanding voltage amount against the electrostatic discharge which is standardized, e.g., by the Japanese Industrial Standard, a gate width with several hundreds of micrometers is needed. Therefore, a problem arises that the area of the protection element becomes large. A circuit designer may design the protection element so that it has a interleaved comblike form as illustrated in FIG. 2 to reduce the element area. As shown in FIG. 2, a gate electrode 210 and a common wiring 212 are formed. The common wiring 212 is commonly connected to a source region, the gate electrode 210 and a substrate. Furthermore, a drain wiring 214, which is connected to a drain region, is formed. The gate electrode 210, the common wiring 212 and the drain wiring 214 are shaped into the comblike form.
The protection element includes contact holes where conductive materials are formed therein. The conductive materials connect the source region to the common wiring 212. The conductive materials also connect the drain region to the drain wiring 214. The conductive materials also connect the gate electrode to the common wiring 212.
Therefore, the size of the source and the drain regions must be formed in consideration of the need for an alignment margin when the contact holes are formed.
Consequently, there has been a need for an improved semiconductor device.